MSOP_INIT_CPU(D2psm)
MSOP_INIT_CPU --
initialization when CPU is brought online
Synopsis
void pfxinit_cpu(void)
Description
MSOP_INIT_CPU is called when a CPU is brought online,
either for the first time or after being brought offline. It allows the
PSM the chance to initialize any per-CPU states.
On any given CPU, MSOP_INIT_CPU must be called before
any other MSOP or delivery function.
Interrupts are disabled on the CPU when MSOP_INIT_CPU is
called.
MSOP_INIT_CPU must initialize the following:
interrupt control system-
Interrupts for any attached
interrupt slots may be delivered to the CPU at this point. (See
MSOP_INTR_ATTACH(D2psm).)
ms_event_t events are also enabled at this point. Once events are
enabled at the CPU by the core kernel (after a return from
MSOP_INIT_CPU), the system will begin processing interrupts and
PSM interrupt delivery functions will be called.
free-running high-resolution clock-
This clock is used by
MSOP_TIME_GET(D2psm).
It may be one global clock or a local clock
for each CPU.
heartbeat tick clock event generation-
The PSM must post MSOP_EVENT_TICK_1
events (generated by clock 1) once
per tick on each CPU on which MSOP_INIT_CPU has been called,
until
MSOP_OFFLINE_PREP(D2psm)
is called. If the hardware supports it,
the delivery of ticks should be staggered so all CPUs do not run
their tick handlers at the same time.
The core kernel variable os_tick_period
(see
Intro(D4psm))
specifies the tick period
for MSOP_EVENT_TICK_1 events. MSOP_EVENT_TICK_2 events
should not be posted unless indicated by a MSOP_EVENT_TICK_2 call.
The average period of clock ticks (both clock 1 and clock 2) must be within
plus or minus 0.5% of the requested period, that is, with at most
7.5 minutes per day
error. Individual ticks, however, may be posted as much as 45% of the tick
period off the nominal end of period.
Many platforms do not have separate hardware sources for clock 1 and clock 2.
Some have only one global time source, instead of per-CPU timers.
In such cases, the PSM must emulate what is not provided in hardware.
To emulate per-CPU ticks from a single global tick, the PSM
should post the current CPU's tick directly during the global tick
interrupt, and distribute ticks to the other CPUs using cross-processor
interrupts. This reproduces the effect of calling, for example,
MSOP_XPOST(MS_CPU_ALL_BUT_ME, MS_EVENT_TICK_1).
Notes
If an operating system needs to perform some tick processing more coarsely
than on a per-CPU basis, for example, global tick processing or
per-CG tick processing, it can do this from the per-CPU
tick events without any cross-processor traffic or bus locking. The simple
algorithm for this is to pick a specific CPU to handle each coarser
tick sequence, for example, CPU 0 for global processing and
each SBSP for per-CG processing. During the chosen CPU's
local tick, it would do both local processing and its additional coarser
processing. A more advanced algorithm that balances the load across CPUs
would involve having each CPU's tick handler keep a local tick count.
The tick handler would then do per-group work when the current count modulo the group size is
equal to this CPU's relative ID number within the group. All
CPUs would have to co-ordinate to reset their counts during an online
or offline procedure.
Arguments
None.
Return values
None.
Usage
Hardware applicability
All.
Version applicability
psm:
2
References
MSOP_INTR_ATTACH(D2psm),
MSOP_TIME_GET(D2psm),
MSOP_OFFLINE_PREP(D2psm)
19 June 2005
© 2005 The SCO Group, Inc. All rights reserved.
OpenServer 6 and UnixWare (SVR5) HDK - 19 June 2005