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Glossary
atomic transaction an I/O bus transaction which is indivisible with respect to other transactions. Other concurrent transactions will either see the state of the referenced memory (or device register) as it was before the atomic transaction or after it, but not an intermediate value. Further, the adapter being accessed will see the access as exactly one transaction. For example, a WRITE4 transaction (4-byte write) is atomic if no observer of the same address can see a mixture of old and new byte values, and two WRITE4's for the same address are atomic with respect to each other if one overwrites the other without mixing byte values.
bridge driver see bus bridge driver.
bridge metalanguage see bus bridge metalanguage.
bus address see card-relative address.
bus bridge hardware which connects one kind of bus to another. For example, the bridge(s) between the PMI and primary I/O bus(es), or between a primary I/O bus and an attached (secondary) I/O bus. Bus bridges may be transparent to the software or may require more active participation of a bus bridge driver.
bus bridge driver device driver software responsible for managing a bus bridge.
bus bridge metalanguage a UDI metalanguage which covers registration and de-registration of interrupt handlers plus the delivery of bus-related events. It is (currently) subdivided into four interface sets, one for each of four roles: the bridge, the device, the interrupt handler and the interrupt dispatcher.
card-relative address a physical memory address from the point of view of an adapter card's DMA engine. Such an address is used by the device to access main system memory, but may go through a translation process (in hardware) before reaching the memory.
DMA Direct Memory Access by an I/O card to system memory without host processor intervention.
interrupt dispatcher a driver which is responsible for managing interrupt control and routing hardware.
interrupt handler a driver that is responsible for the interrupt-related, device-specific, software control and management of interrupt-associated hardware.
interrupt router the entity, transparent to the interrupt handler driver, that steers an interrupt along a specific signal path between the interrupting device and an interrupt slot on a particular interrupt controller.
interrupt slot the index of an interrupt request source (starting from zero) relative to a particular interrupt controller. In UDI, the slot number is found in the device's instance attributes.
interrupt source a specific interrupt request line (or source ID, for messaged based interrupts) through which a device signals its asynchronous events. Depending on the interrupt routing, one or more interrupt sources may share the same interrupt slot. Multiple interrupt sources sharing the same interrupt slot is known as shared interrupts.
ISA 1) Instruction Set Architecture. Defines the binary machine language syntax and semantics for a particular type of processor or processor family.
2) Industry Standard Architecture. An I/O bus type originally designed for the IBM AT and used in many PCs.
PCI Peripheral Control Interconnect. A specific type of I/O bus.
PIO Programmed-I/O; i.e. transfer of data between the external device and processor memory under direct program control of the CPU. See DMA for contrast.
PMI Processor-Memory Interconnect: the bus or interconnect that links the host CPU with system memory and primary I/O bus bridges.
scatter-gather (scgth) element . a single address/length pair associated with a scatter/gather structure, that identifies one piece of data buffer memory which is contiguous with respect to card-relative addresses.
scatter-gather (scgth) segment an array of one or more scatter/gather elements. Each scatter/gather structure references one or more scatter/gather segments, as necessary to address the entire data buffer. The memory containing a scatter/gather segment is itself contiguous with respect to card-relative addresses.
scatter-gather (scgth) structure a driver-visible UDI structure that reflects the card-relative addresses of a possibly physically discontiguous but logically contiguous data buffer, which the driver uses to set up DMA transfers.
shared interrupts see interrupt source.
sync an environment service that synchronizes the hosts view of memory with an I/O card's view. This includes cache flushing and purging, flushing buffers in bus bridges, etc.
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